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| Features * * * * * * * * * * * * * * Processor Bus Frequency Up to 66 MHz and 83.3 MHz 64-bit Data Bus and 32-bit Address Bus L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes Provides Support for Either Asynchronous SRAM, Burst SRAM or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates at 20 to 33 MHz, 3.3V/5.0V-compatible IEEE 1149.1-compliant, JTAG Boundary-scan Interface PD Max = 1.7 Watts (66 MHz), Full Operating Conditions Nap, Doze and Sleep Modes Reduce Power Consumption Fully Compliant with MIL-STD-883 Class Q or According to Atmel Standards Upscreenings Based on Atmel Standards Full Military Temperature Range (-55C TC +125C) - Industrial Temperature Range (-40C TC +110C) VCC = 3.3V 5% Available in a 303-ball CBGA or a 303-ball CBGA with Solder Column Interposer (SCI) (CI-CGA) Package PCI Bridge/ Memory Controller TSPC106 Description The TSPC106 provides an integrated, high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or up to a total of four additional 60x processors, the PCI bus and main memory. PCI support allows system designers to rapidly design systems using peripherals already designed for PCI. The TSPC106 uses an advanced 3.3V CMOS-process technology and maintains full interface compatibility with TTL devices. The TSPC106 integrates system testability and debugging features via JTAG boundary-scan capability. G suffix CBGA 303 Ceramic Ball Grid Array GS suffix CICGA 303 Ceramic Ball Grid Array with Solder Column Interposer (SCI) Rev. 2102B-HIREL-02/02 1 Figure 1. TSPC106 Block Diagram L2 Cache Interface L2 Memory Interface Memory Power Management 60x Processor Interface 60x Bus Error/Interrupt Control Target Master Configuration Registers PCI Interface PCI Bus Functional Description The TSPC106 provides a PowerPC(R) microprocessor CHRP-compliant bridge between the PowerPC microprocessor family and the PCI bus. CHRP is a set of specifications that defines a unified personal computer architecture and brings the combined advantages of the Power Macintosh(R) platform and the standard PC environment to both system vendors and users. PCI support allows system designers to rapidly design systems using peripherals already designed for PCI and other standard interfaces available in the personal computer hardware environment. These open specifications make it easier for system vendors to design computers capable of running multiple operating systems. The TSPC106 integrates secondary cache control and a high-performance memory controller. The TSPC106 uses an advanced 3.3V CMOS process technology and is fully compatible with TTL devices. The TSPC106 supports a programmable interface to a variety of PowerPC microprocessors operating at select bus speeds. The 60x address bus is 32 bits wide; the data bus is 64 bits wide. The 60x processor interface of the TSPC106 uses a subset of the 60x bus protocol, supporting single-beat and burst data transfers. The address and data buses are decoupled to support pipelined transactions. 2 TSPC106 2102B-HIREL-02/02 TSPC106 The TSPC106 provides support for the following configurations of 60x processors and L2 cache: * * * Up to four 60x processors with no L2 cache A single 60x processor plus a direct-mapped, lookaside L2 cache using the internal L2 cache controller of the TSPC106 Up to four 60x processors plus an externally controlled L2 cache (e.g., the Motorola MPC2604GA integrated L2 lookaside cache) The memory interface controls processor and PCI interactions to main memory and is capable of supporting a variety of configurations using DRAM, EDO, or SDRAM and ROM or Flash ROM. The PCI interface of the TSPC106 complies with the PCI local bus specification Revision 2.1 and follows the guidelines in the PCI System Design Guide Revision 1.0 for host bridge architecture. The PCI interface connects the processor and memory buses to the PCI bus to which I/O components are connected. The PCI bus uses a 32-bit multiplexed address/data bus plus various control and error signals. The PCI interface of the TSPC106 functions as both a master and target device. As a master, the 106 supports read and write operations to the PCI memory space, the PCI I/O space and the PCI configuration space. The TSPC106 also supports PCI specialcycle and interrupt-acknowledge commands. As a target, the TSPC106 supports read and write operations to system memory. The TSPC106 provides hardware support for four levels of power reduction: doze, nap, sleep and suspend. The design of the TSPC106 is fully static, allowing internal logic states to be preserved during all power saving modes. 3 2102B-HIREL-02/02 Pin Description Figure 2. TSPC106 in 303-ball CBGA Package 16 W DL26 15 DL28 14 DL30 13 DH31 12 DH29 11 DH27 10 DH25 9 DH23 8 DH21 7 DH19 6 DH17 5 DH15 4 DH13 3 DH11 2 DH9 1 DH7 V DL24 DL27 DL29 DL31 DH30 DH28 DH26 DH24 DH20 DH18 DH16 DH14 DH12 DH10 DH8 DL22 U MA1/ SDBA0/ AR9 MA2/ SDMA2/ AR10 MA3/ SDMA3/ AR11 MA5/ SDMA5/ AR13 MA6/ SDMA6/ AR14 MA8/ SDMA8/ AR16 DL23 DL25 DL14 PLL2 PLL0 DL12 DL10 DL4 DL2 DL0 DOE/ DBGL2 DBG1 DH6 DL21 DL20 T WE DH0 DL15 PLL3 PLL1 DL13 DL11 DL3 DL1 TV/ BR2 BA0/ BR3 HIT DIRTY_IN/ BR1 ADS/ DALE/ BRL2 DWE0/ DBG2 DL19 DCS/ BG3 R RCS0 DH2 DH1 DL16 VSS VDD DL9 DL5 VSS VDD TWE/ BG2 DIRTY_OUT/ BG1 BA1/ BAA BGL2 A0 TS P MA4/ SDMA4/ AR12 MA0/ SDBA1/ SDMA0/ AR0 MA7/ SDMA7/ AR15 MA9/ SDMA9/ AR17 DH4 DH3 VSS VDD VSS DL8 DL6 VDD VSS VDD A1 XATS/ SDMA1 N DL17 DH5 VDD VSS VDD DL7 DH22 VSS VDD VSS LBCLAIM CI A2 TA M RAS0/ CS0 DL18 VSS VDD VSS NC NC VDD VSS VDD WT GBL A3 TT4 L HRST QACK RAS1/ CS1 VDD CKO/ DWE2 RAS5/ CS5 VSS VDD VSS SYSCLK DBG0 TBST BR0 A4 TT3 K MA11/ MA10/ SDMA11/ SDMA10/ AR19 AR18 MA12/ SDMA12/ AR20 CAS0/ DQM0 RAS3/ CS3 RAS2/ CS2 RAS4/ CS4 RAS7/ CS7 VDD AVDD VSS VDD A9 A8 A7 BG0 A5 TT2 J PPEN RCS1 RAS6/ CS6 MCP DBGLB/ CKE VSS VDD VSS A11 A6 A13 A12 A10 TEA H QREQ CAS1/ DQM1 SUSPEND TRST VSS DWE1/ DBG3 PIRQ/ SDRAS NC NC VDD VSS VDD A15 A14 A16 TT1 G CAS2/ DQM2 RTC CAS4/ DQM4 CAS5/ DQM5 VDD LSSD_ MODE VDD PAR LOCK VSS VDD VSS TSIZ1 TSIZ0 A17 TT0 F BCTL0 BCTL1 CAS6/ DQM6 TCK VSS VDD VSS PERR DEVSEL VDD VSS VDD A21 TSIZ2 ARTRY A18 E CAS3/ DQM3 NMI CAS7/ DQM7 MDLE/ SDCAS TDO VSS VDD SERR IRDY VSS VDD A31 A29 A22 A20 A19 D PAR0/ AR1 PAR2/ AR3 PAR1/ AR2 TMS FOE AD28 AD24 AD21 AD17 AD14 AD10 C/BE0 AD4 AD0 A30 AACK A23 C PAR3/ AR4 PAR5/ AR6 AD30 AD26 AD23 AD19 C/BE2 C/BE1 AD12 AD8 AD6 AD2 A27 A25 A24 B PAR4/ AR5 PAR7/ AR8 AD1 TDI AD7 AD11 AD15 TRDY AD18 AD22 AD25 AD29 REQ ISA_MASTER/ BERR A28 A26 A PAR6/ AR7 GNT AD3 AD5 AD9 AD13 FRAME STOP AD16 AD20 C/BE3 AD27 AD31 FLSHREQ MEMACK 4 TSPC106 2102B-HIREL-02/02 TSPC106 Figure 3. Pin Assignments Shading Ley VIEW NC No connect VDD Power Supply Positive VSS Power Supply Ground AVDD Clock Power Supply Positive (K9) Signals Pinout Table 1. TSPC106 Pinout in 303-ball CBGA Package Signal Name Pin Number 60x Processor Interface Signals A[0:31] AACK ARTRY BG0 BG1 (DIRTY_OUT) BG2 (TWE) BG3 (DCS) BR0 BR1 (DIRTY_IN) BR2 (TV) BR3 (BA0) CI DBG0 DBG1 (TOE) DBG2 (DWE0) DBG3 (DWE1) DBGLB (CKE) DH[0:31] R2, P2, N2, M2, L2, K2, J5, K4, K5, K6, J2, J6, J3, J4, H3, H4, H2, G2, F1, E1, E2, F4, E3, D1, C1, C2, B1, C3, B2, E4, D3, E5 D2 F2 K3 R4 R5 T1 L3 T3 T6 T5 N3 L5 U4 P3 H11 J10 T14, R13, R14, P13, P14, N13, U3, W1, V2, W2, V3, W3, V4, W4, V5, W5, V6, W6, V7, W7, V8, W8, N8, W9, V9, W10, V10, W11, V11, W12, V12, W13 U6, T7, U7, T8, U8, R8, P8, N9, P9, R9, U9, T9, U10, T10, U13, T13, R12, N14, M13, T2, U1, U2, V1, U15, V16, U14, W16, V15, W15, V14, W14, V13 M3 N4 High Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low High I/O I/O I/O Output Output Output Output Input Input Input Input I/O Output Output Output Output Output I/O Active I/O DL[0:31] High I/O GBL LBCLAIM Low Low I/O Input 5 2102B-HIREL-02/02 Table 1. TSPC106 Pinout in 303-ball CBGA Package (Continued) Signal Name MCP TA TBST TEA TS TSIZ[0:2] TT[0:4] WT XATS (SDMA1) Pin Number J11 N1 L4 J1 R1 G3, G4, F3 G1, H1, K1, L1, M1 M4 P1 L2 Cache Interface Signals ADS/DALE/BRL2 BA0 (BR3) BA1/BAA/BGL2 DBGL2/DOE DCS (BG3) DIRTY_IN (BR1) DIRTY_OUT (BG1) DWE0 (DBG2) DWE1 (DBG3) DWE2 (CKO) HIT TOE (DBG1) TV (BR2) TWE (BG2) R3 T5 P4 U5 T1 T3 R4 P3 H11 L11 T4 U4 T6 R5 Memory Interface Signals BCTL [0:1] BERR (ISA_MASTER) CAS/DQM[0:7] CKE/DBGLB FOE MA0/SDBA1/SDMA0/AR0 SDMA1 (XATS) MA1/SDBA0/AR9 MA[2:12]/SDMA[2:12]/AR[10:2 0] MDLE/SDCAS F16, F15 B3 J15, H15, G16, E16, G14, G13, F14, E14 J10 D13 N15 P1 U16 T16, R16, P15, P16, N16, M15, M16, L15, K15, K16, J16 E13 Low Low Low High Low High High High High Low Output Input Output Output Output Output Output Output Output Output Low Low Low Low Low Low Low Low Low Low Low Low High Low Output Output Output Output Output Input Output Output Output Output Input Output I/O Output Active Low Low Low Low Low High High Low Low I/O Output I/O I/O Output I/O I/O I/O I/O Input 6 TSPC106 2102B-HIREL-02/02 TSPC106 Table 1. TSPC106 Pinout in 303-ball CBGA Package (Continued) Signal Name PAR[0:7]/AR[1:8] PPEN RAS/CS[0:7] RCS0 RCS1 RTC SDRAS (PIRQ) WE Pin Number D16, D15, C16, C15, B16, C14, A16, B15 J14 M14, L13, K13, K14, K12, L10, J12, K11 R15 J13 G15 H10 T15 PCI Interface Signals(2) AD[31:0](2) A4, C13, B5, D12, A5, C12, B6, D11, C11, B7, D10, A7, C10, B8, D9, A8, B10, D8, A11, C7, B11, D7, A12, C6, B12, C5, A13, D5, A14, C4, B14, D4 A6, C9, C8, D6 F8 A3 A10 A15 E8 B3 G8 A2 G9 F9 H10 B4 E9 A9 B9 Interrupt, Clock and Power Management Signals CK0 (DWE2) HRST NMI QACK QREQ SYSCLK SUSPEND L11 L16 E15 L14 H16 L6 H14 Test/Configuration Signals High Low High Low Low Clock Low Output Input Input Output Input Input Input Active High Low Low Low Low High Low Low I/O I/O Output Output I/O Output Input Output Output High Low Low Low Low Low Low Low Low Low High Low Low Low Low Low Low I/O I/O I/O Input I/O Input I/O Input Input Output I/O I/O Output Output I/O I/O I/O C/BE[3:0](2) DEVSEL FLSHREQ FRAME GNT IRDY ISA_MASTER (BERR) LOCK MEMACK PAR PERR PIRQ (SDRAS) REQ SERR STOP TRDY 7 2102B-HIREL-02/02 Table 1. TSPC106 Pinout in 303-ball CBGA Package (Continued) Signal Name PLL[0:3] TCK TDI TDO TMS TRST Pin Number U11, T11, U12, T12 F13 B13 E12 D14 H13 Power and Ground Signals AVDD LSSD_MODE(3) VDD VSS NC Notes: K9 G11 E10, E6, F11, F5, F7, G10, G12, G6, H5, H7, K10, K7, L12, M11, M5, M7, N10, N12, N6, P11, P5, P7, R10, R6, J8, L8 E11, E7, F10, F12, F6, G5, G7, H12, H6, J7, L7, M10, M12, M6, N11, N5, N7, P10, P12, P6, R11, R7, K8, J9, L9 H8, H9, M8, M9 1. Some signals have dual functions and are shown more than once in this table. 2. All PCI signals are in little-endian bit order. 3. This test signal is for factory use only. It must be pulled up to VDD for normal device operation. High Low High Low - Clock Input Power Ground - Active High Clock High High High Low I/O Input Input Input Output Input Input Signal Description The signals on the TSPC106 are grouped as follows: * * * * * * * 60x processor interface signals L2 cache/multiple processor interface signals Memory interface signals PCI interface signals Interrupt, clock and power management signals IEEE 1149.1 interface signals Configuration signals A bar over a signal name indicates that the signal is active low, for example, address retry (ARTRY) and transfer start (TS). Active-low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low such as tag valid (TV) and nonmaskable interrupt (NMI) are referred to as asserted when they are high and negated when they are low. For multiple-function signals, outlined signal names refer to the alternate function(s) of the signal being described. For example, the L2 controller signal, (tag output enable TOE), has the alternate function data bus grant 1 (DBG1) when the TSPC106 is configured for a second 60x processor. Note: Note: 8 TSPC106 2102B-HIREL-02/02 TSPC106 Figure 4. Symbol AD[31:0] C/BE[3:0] PAR TRDY IRDY FRAME STOP 32 4 1 1 1 1 1 1 1 2 1 1 1 1 1 1 8 8 1 1 12 8 1 2 1 1 2 1 2 1 1 1 1 1 1 1 1 4 1 1 1 1 32 5 3 1 3 1 1 1 64 1 1 1 2 1 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 BR0 BG0 TS XATS A[0:31] TT[0:4] TSIZ[0:2] TBST WT, CI, GBL AACK ARTRY DBG0 (1) PCI Interface LOCK DEVSEL SERR, PERR REQ GNT FLSHREQ MEMACK ISA_MASTER PIRQ RAS[0:7] CAS[0:7] WE MA0/AR0 MA[1:12]/AR[9:20] PAR[0:7]/AR[1:8] FOE (1) 60x Processor Interface DH[0:31], DL[0:31] TA LBCLAIM DBGLB MCP, TEA ADS/DALE/BRL2 BAA/BA1/BGL2 DOE/DBGL2 DWE[0:2]/DBG2, DBG3, CKO HIT DCS/BG3 BA0/BR3 TWE/BG2 TV/BR2 DIRTY_IN/BR1 DIRTY_OUT/BG1 TOE/DBG1 TDO TDI TCK TMS TRST (1) Memory Interface MDLE, PPEN RCS1 RCS0 (1) L2 Cache/ Multiple Processor Interface BCTL0, BCTL1 RTC SYSCLK, CKO(1) HRST Interrupt, Clock and Power Management Signals NMI QREQ QACK SUSPEND DBG0 FOE (1) (1) IEEE 1149.1 JTAG Interface Configuration RCS0 PLL[0:3] Note: Some signals have dual functions and are shown more than once in this figure. 9 2102B-HIREL-02/02 60x Processor Interface Signals Table 2. 60x Processor Interface Signals Signal A[0:31] Signal Name Address bus Number of Pins 32 I/O O I Signal Description Specifies the physical address for 60x bus snooping. Specifies the physical address of the bus transaction. For burst reads, the address is aligned to the critical double-word address that missed in the instruction or data cache. For burst writes, the address is aligned to the double-word address of the cache line being pushed from the data cache. Indicates that the address tenure of a transaction is terminated. On the cycle following the assertion of AACK, the bus master releases the address-tenure-related signals to a high impedance state and samples ARTRY. Indicates that an externally-controlled L2 cache is terminating the address tenure. On the cycle following the assertion of AACK, the bus master releases the address-tenure-related signals to a high impedance state and samples ARTRY. Indicates that the initiating 60x bus master must retry the current address tenure. During a snoop operation, indicates that the 60x either requires the current address tenure to be retried due to a pipeline collision or needs to perform a snoop copy-back operation. During normal 60x bus cycles in a multiprocessor system, indicates that the other 60x or external L2 controller requires the address tenure to be retried. Indicates that the primary 60x may, with the proper qualification, begin a bus transaction and assume mastership of the address bus. Indicates that the primary 60x requires the bus for a transaction. Indicates that an access is caching-inhibited. Indicates that the 60x may, with the proper qualification, assume mastership of the data bus. Indicates that the 60x processor is prepared to accept data and the local bus slave should drive the data bus. AACK Address acknowledge 1 O I ARTRY Address retry 1 O I BG0 BR0 CI DBG0 DBGLB Bus grant 0 Bus request 0 Cache inhibit Data bus grant 0 Local bus slave data bus grant 1 1 1 1 1 O I I/O O O 10 TSPC106 2102B-HIREL-02/02 TSPC106 Table 2. 60x Processor Interface Signals (Continued) Signal DH[0:31], DL[0:31] Signal Name Data bus Number of Pins 64 I/O Signal Description The data bus is comprised of two halves - data bus high (DH[0:31]) and data bus low (DL[0:31]). The data bus has the following byte lane assignments: Data Byte DH[0:7] DH[8:15] DH[16:23] DH[24:31] DL[0:7] DL[8:15] DL[16:23] DL[24:31] O I GBL LBCLAIM MCP TA Global Local bus slave cycle claim Machine check Transfer acknowledge 1 1 1 1 I/O I O O Byte Lane 0 1 2 3 4 5 6 7 Represents the value of data being driven by the TSPC106. Represents the state of data being driven by a 60x processor, the local bus slave, the L2 cache or the memory subsystem. Indicates that an access is global and hardware needs to enforce coherency. Indicates that the local bus slave claims the transaction and is responsible for driving TA during the data tenure. Indicates that the TSPC106 detected a catastrophic error and the 60x processor should initiate a machine check exception. Indicates that the data has been latched for a write operation or that the data is valid for a read operation, thus terminating the current data beat. If it is the last (or only) data beat, this also terminates the data tenure. Indicates that the external L2 cache or local bus slave has latched data for a write operation or is indicating the data is valid for a read operation. If it is the last (or only) data beat, then the data tenure is terminated. Indicates that a burst transfer is in progress. Indicates that a burst transfer is in progress. Indicates that a bus error has occurred. Assertion of TEA terminates the transaction in progress. An unsupported memory transaction, such as a direct-store access or a graphics read or write, causes the assertion of TEA (provided TEA is enabled). Indicates that the TSPC106 has started a bus transaction and that the address and transfer attribute signals are valid. Note that the TSPC106 only initiates a transaction to broadcast the address of a PCI access to memory for snooping purposes. Indicates that a 60x bus master has begun a transaction and that the address and transfer attribute signals are valid. I TBST Transfer burst 1 O I TEA Transfer error acknowledge 1 O TS Transfer start 1 O I 11 2102B-HIREL-02/02 Table 2. 60x Processor Interface Signals (Continued) Signal TSIZ[0:2] Signal Name Transfer size Number of Pins 3 I/O O I TT[0:4] Transfer type 5 O I WT XATS Write-through Extended address transfer start 1 1 I/O I Signal Description Specifies the data transfer size for the 60x bus transaction. Specifies the data transfer size for the 60x bus transaction. Specifies the type of 60x bus transfer in progress. Specifies the type of 60x bus transfer in progress. Indicates that an access is write-through. Indicates that the 60x has started a direct-store access (using the extended transfer protocol). Since direct-store accesses are not supported by the TSPC106, the TSPC106 automatically asserts when TEA and XATS are asserted (provided TEA is enabled). L2 Cache/Multiple Processor Interface Signals Internal L2 Controller Signals The TSPC106 provides support for either an internal L2 cache controller or an external L2 cache controller and/or additional 60x processors. Table 3 lists the interface signals for the internal L2 controller and provides a brief description of their functions. The internal L2 controller supports either burst SRAMs or asynchronous SRAMs. Some of the signals perform different functions depending on the SRAM configuration. Table 3. Internal L2 Controller Signals Signal ADS DALE BRL2 BA0 BR3 BA1 BAA BGL2 BAA BA1 BGL2 DALE ADS BRL2 DCS BG3 DIRTY_IN BR1 DIRTY_OUT BG1 Signal Name Address strobe Number of Pins 1 I/O O Signal Description For a burst SRAM configuration, indicates to the burst SRAM that the address is valid to be latched. For an asynchronous SRAM configuration, indicates bit 0 of the burst address counter. For an asynchronous SRAM configuration, indicates bit 1 of the burst address counter. For a burst SRAM configuration, indicates that the burst RAMs should increment their internal addresses. For an asynchronous SRAM configuration, indicates that the external address latch should latch the current 60x bus address. Enables the L2 data RAMs for a read or write operation. Indicates that the selected L2 cache line is modified. The polarity of DIRTY_IN is programmable. Indicates that the L2 cache line should be marked as modified. The polarity of DIRTY_OUT is programmable. Burst address 0 Burst address 1 1 1 I/O O Bus address advance Data address latch enable Data RAM chip select Dirty in Dirty out 1 O 1 O 1 1 1 O I O 12 TSPC106 2102B-HIREL-02/02 TSPC106 Table 3. Internal L2 Controller Signals (Continued) Signal DOE DBGL2 DWE[0:2] DBG2 DBG3 HIT TOE DBG1 TV BR2 TWE BG2 Signal Name Data RAM output enable Data RAM write enable Hit Tag output enable Tag valid Tag write enable Number of Pins 1 3 I/O O O Signal Description Indicates that the L2 data RAMs should drive the data bus. Indicates that a write to the L2 data RAMs is in progress. Multiple pins are provided to reduce loading. Indicates that the L2 cache has detected a hit. The polarity of HIT is programmable. Indicates that the tag RAM should drive the L2 tag address onto the address bus. Indicates that the current L2 cache line should be marked valid. The polarity of TV is programmable. Indicates that the L2 tag address, valid, and dirty bits should be updated. 1 1 1 1 I O I/O O External L2 Controller Signals When an external L2 cache controller is used instead of the internal L2 cache controller, four signals change their functions. Table 4. External L2 Controller Signals Signal BGL2 BA1 BAA BRL2 ADS DALE DBGL2 DOE HIT Signal Name External L2 bus grant External L2 bus request External L2 data bus grant External L2 hit Number of Pins 1 I/O O Signal Description Indicates that the external L2 controller has been granted mastership of the 60x address bus. Indicates that the external L2 controller requires mastership of the 60x bus for a transaction. Indicates that the external L2 controller has been granted mastership of the 60x data bus. Indicates that the current transaction is claimed by the external L2 controller. The external L2 controller will assert AACK and TA for the transaction. 1 I 1 1 O I 13 2102B-HIREL-02/02 Multiple Processor Signals When a system implementation uses more than one 60x processor, nine of the internal L2 cache controller signals change their functions. Note that in a multi-processor system, with the exception of the bus grant, bus request and data bus grant signals, all of the 60x processor interface signals are shared by all 60x processors. Table 5. Multiple Processor Signals Signal BG1 DIRTY_OUT BG2 TWE BG3 DCS BR1 DIRTY_IN BR2 TV BR3 BA0 DBG1 TOE DBG2 DWE0 DBG3 DWE1 Signal Name Bus grant 1 Bus grant 2 Bus grant 3 Bus request 1 Bus request 2 Bus request 3 Data bus grant 1 Data bus grant 2 Data bus grant 3 Number of Pins 1 1 1 1 1 1 1 1 1 I/O O O O I I I O O O Signal Description Indicates that processor 1 may, with the proper qualification, begin a 60x bus transaction and assume mastership of the address bus. Indicates that processor 2 may, with the proper qualification, begin a 60x bus transaction and assume mastership of the address bus. Indicates that processor 3 may, with the proper qualification, begin a 60x bus transaction and assume mastership of the address bus. Indicates that processor 1 requires mastership of the 60x bus for a transaction. Indicates that processor 2 requires mastership of the 60x bus for a transaction. Indicates that processor 3 requires mastership of the 60x bus for a transaction. Indicates that processor 1 may, with the proper qualification, assume mastership of the 60x data bus. Indicates that processor 2 may, with the proper qualification, assume mastership of the 60x data bus. Indicates that processor 3 may, with the proper qualification, assume mastership of the 60x data bus. 14 TSPC106 2102B-HIREL-02/02 TSPC106 Memory Interface Signals Table 6 lists the memory interface signals and provides a brief description of their functions. The memory interface supports either standard DRAMs or EDO DRAMs, and either standard ROMs or Flash ROMs. Some of the memory interface signals perform different functions depending on the RAM and ROM configurations. Table 6. Memory Interface Signals Signal AR0 MA0 Signal Name ROM address 0 Number of Pins 8 I/O O Signal Description Represents address bit 0 of the 8-bit ROM/Flash. Note that AR0 is only supported for ROM bank 0 when configured for an 8-bit ROM/Flash data bus width. The extra address bit allows for up to 2 Mbytes of ROM when using the 8-bit wide data path. Bits 1 - 8 of the ROM address are provided by AR[1:8] and bits 9 - 20 of the ROM address are provided by AR[9:20]. Represents bits 1 - 8 of the ROM/Flash address. The other ROM address bits are provided by AR0 and AR[9:20]. Represents bits 9 - 20 of the ROM/Flash address (the 12 lowest order bits, with AR20 as the least significant bit (lsb)). Bits 0 - 8 of the ROM address are provided by AR0 and AR[1:8]. Used to control external data bus buffers (directional control and highimpedance state) between the 60x bus and memory. Note that external data buffers may be optional for lightly loaded data buses, but buffers are required whenever an L2 cache and ROM/Flash (on the 60x/memory bus) are both in the system or when ECC is used. Indicates a memory column address is valid and selects one of the columns in the row. CAS0 connects to the most significant byte select. CAS7 connects to the least significant byte select. Enables Flash output for the current read access. Represents the row/column multiplexed physical address for DRAMs or EDOs (MA0 is the most significant address bit; MA12 is the least significant address bit). Note that MA0 also functions as the ROM address signal AR0 and MA[1:12] function as the ROM address signals AR[9:20]. Enables the external, latched data buffer for read operations, if such a buffer is used in the system. Represents the byte parity or ECC being written to memory (PAR0 is the most significant bit). Represents the byte parity or ECC being read from memory (PAR0 is the most significant bit). Enables external parity/ECC bus buffer or latch for memory read operations. Indicates a memory row address is valid and selects one of the rows in the bank. Selects ROM/Flash bank 0 for a read access or Flash bank 0 for a read or write access. Selects ROM/Flash bank 1 for a read access or Flash bank 1 for a read or write access. External clock source for the memory refresh logic when the TSPC106 is in the suspend power-saving mode. Enables writing to DRAM, EDO or Flash. AR[1:8] PAR[0:7] AR[9:20] MA[1:12] BCTL[0:1] ROM address 1 - 8 ROM address 9 - 20 Buffer control 0 - 1 8 12 O O 2 O CAS[0:7] Column address strobe 0 - 7 Flash output enable Memory address 0 - 12 8 O FOE MA0 MA[1:12] AR0 AR[9:20] MDLE PAR[0:7] AR[1:8] 1 13 O O Memory data latch enable Data parity/ECC 1 8 O O I PPEN RAS[0:7] RCS0 RCS1 RTC WE Parity path read enable Row address strobe 0 - 7 ROM/Flash bank 0 select ROM/Flash bank 1 select Real-time clock Write enable 1 8 1 1 1 1 O O O O I O 15 2102B-HIREL-02/02 PCI Interface Signals Table 7 lists the PCI interface signals and provides a brief description of their functions. Note that the bits in Table 7 are referenced in little-endian format. The PCI specification defines a sideband signal as any signal, not part of the PCI specification, that connects two or more PCI-compliant agent, and has meaning only to those a g e n t s. Th e TS PC 1 0 6 im p le me n t s fo u r P C I sid e b a n d sig n a ls -FL S H R EQ , ISA_MASTER, MEMACK and PIRQ. Table 7. PCI Interface Signals Signal AD[31:0] Signal Name Address/data Number of Pins 32 I/O I/O Signal Description Represents the physical address during the address phase of a transaction. During the data phase(s) of a PCI transaction, AD[31:0] contain data. AD[7:0] define the least significant byte and AD[31:24] the most significant byte. During the address phase, C/BE[3:0] define the PCI bus command. During the data phase, C/BE[3:0] are used as byte enables. Byte enables determine which byte lanes carry meaningful data. C/BE0 applies to the least significant byte. During the address phase, C/BE[3:0] indicates the PCI bus command that another master is sending. During the data phase C/BE[3:0] indicate which byte lanes are valid. Indicates that the TSPC106 has decoded the address and is the target of the current access. Indicates that some PCI agent (other than the TSPC106) has decoded its address as the target of the current access. Indicates that a device needs to have the TSPC106 flush all of its current operations. Indicates that the TSPC106, acting as a PCI master, is initiating a bus transaction. Indicates that another PCI master is initiating a bus transaction. Indicates that the TSPC106 has been granted control of the PCI bus. Note that GNT is a point-to-point signal. Every master has its own GNT SIGNAL. Indicates that the TSPC106, acting as a PCI master, can complete the current data phase of a PCI transaction. During a write, the TSPC106 asserts IRDY to indicate that valid data is present on AD[31:0]. During a read, the TSPC106 asserts IRDY to indicate that it is prepared to accept data. Indicates another PCI master is able to complete the current data phase of the transaction. Indicates that an ISA master is requesting system memory. Indicates that a master is requesting exclusive access to memory, which may require multiple transactions to complete. Indicates that the TSPC106 has flushed all of its current operations and has blocked all 60x transfers except snoop copy-back operations. The TSPC106 asserts MEMACK in response to assertion of FLSHREQ after the flush is complete. C/BE[3:0] Command/byte enable 4 O I DEVSEL Device select 1 O I FLSHREQ FRAME Flush request Frame 1 1 I O I GNT PCI bus grant 1 I IRDY Initializer ready 1 O I ISA_ MASTER LOCK MEMACK ISA master Lock Memory acknowledge 1 1 1 I I O 16 TSPC106 2102B-HIREL-02/02 TSPC106 Table 7. PCI Interface Signals Signal PAR Signal Name Parity Number of Pins 1 I/O O Signal Description Asserted indicates odd parity across the AD[31:0] and C/BE[3:0] signals during address and data phases. Negated indicates even parity. Asserted indicates odd parity driven by another PCI master or the PCI target during read data phases. Negated indicates even parity. Indicates that another PCI agent detected a data parity error. Indicates that another PCI agent detected a data parity error. In emulation mode (see "Address Maps" on page 19), indicates that a PCI write has occurred to system memory that has not been recorded by software. Indicates that the TSPC106 is requesting control of the PCI bus to perform a transaction. Note that REQ is a point-to-point signal. Every master has its own REQ signal. Indicates that an address parity error or some other system error (where the result will be a catastrophic error) was detected. Indicates that another target has detected a catastrophic error. Indicates that the TSPC106, acting as the PCI target, is requesting that the PCI bus master stop the current transaction. Indicates that some other PCI agent is requesting that the PCI initiator stop the current transaction. Indicates that the TSPC106, acting as a PCI target, can complete the current data phase of a PCI transaction. During a read, the TSPC106 asserts TRDY to indicate that valid data is present on AD[31:0]. During a write, the TSPC106 asserts TRDY to indicate that it is prepared to accept data. Indicates that another PCI target is able to complete the current data phase of a transaction. I PERR Parity error 1 O I PIRQ Modified memory interrupt request PCI bus request 1 O REQ 1 O SERR System error 1 O I STOP Stop 1 O I TRDY Target ready 1 O I 17 2102B-HIREL-02/02 Interrupt, Clock and Power Management Signals The TSPC106 coordinates interrupt, clocking, and power management signals across the memory bus, the PCI bus and the 60x processor bus. Table 8. Interrupt, Clock and Power Management Signals Signal CKO DWE2 HRST Signal Name Test clock Number of Pins 1 I/O O Signal Description CKO provides a means to monitor the internal PLL output or the bus clock frequency. The CKO clock should be used for testing purposes only. It is not intended as a reference clock signal. Initiates a complete hard reset of the TSPC106. During assertion, all bi-directional signals are released to a high-impedance state and all output signals are either in a high impedance or inactive state. Indicates that an external device (typically an interrupt controller) has detected a catastrophic error. In response, the TSPC106 asserts MCP on the 60x processor bus. Indicates that the TSPC106 is in a low-power state. All bus activity that requires snooping has terminated and the 60x processor may enter a low-power state. Indicates that a 60x processor is requesting that all bus activity involving snoop operations pause or terminate so that the 60x processor may enter a low-power state. Activates the suspend power-saving mode. SYSCLK sets the frequency of operation for the PCI bus and provides a reference clock for the phase-locked loop (PLL) in the TSPC106. SYSCLK is used to synchronize bus operations. Refer to section "Clocking" on page 19 for more information. Hard reset 1 I NMI Nonmaskable interrupt Quiesce acknowledge Quiesce request 1 I QACK 1 O QREQ 1 I SUSPEND SYSCLK Suspend System clock 1 1 I I IEEE 1149.1 Interface Signals To facilitate system testing, the TSPC106 provides a JTAG test access port that complies with the IEEE 1149.1 boundaryscan specification. Table 9. IEEE 1149.1 Interface Signals Signal TCK Signal Name JTAG test clock Number of Pins 1 I/O I Signal Description Input signals to the test access port (TAP) are clocked in on the rising edge of TCK. Changes to the TAP output signals occur on the falling edge of TCK. The test logic allows TCK to be stopped. The contents of the selected internal instructions or data register are shifted out onto this signal on the falling edge of TCK. TDO will remain in a high-impedance state except when scanning of data is in progress. The value presented on this signal on the rising edge of TCK is clocked into the selected JTAG test instruction or data register. This signal is decoded by the internal JTAG TAP controller to distinguish the primary operation of the test support circuitry. This input causes asynchronous initialization of the internal JTAG TAP controller. TDO JTAG test data output JTAG test data input JTAG test mode select JTAG test reset 1 O TDI TMS TRST 1 1 1 I I I 18 TSPC106 2102B-HIREL-02/02 TSPC106 Configuration Signals Table 10. Configuration Signals Signal DBG0 (1) The configuration signals select the ROM/Flash options, the clock mode of the TSPC106 and how the TSPC106 responds to addresses on the 60x and PCI buses. Number of Pins 1 1 I/O I I Configuration High configures the TSPC106 for address map A. Low configures the TSPC106 for address map B. High configures ROM bank 0 for an 8-bit data bus width. Low configures ROM bank 0 for an 64-bit data bus width. Note that the data bus width for ROM bank 1 is always 64 bits. High/Low - configuration for the PLL clock mode. High indicates ROM is located on the 60x processor/memory data bus. Low indicates ROM is located on the PCI bus. FOE(1) PLL[0:3](2) RCS0 Notes: (1) 4 1 I I 1. The TSPC106 samples these signals during a power-on reset or hard reset operation to determine the configuration. Weak pull-up or pull-down resistors should be used to avoid interference with the normal signal operations. 2. The TSPC106 continuously samples the phase-locked loop (PLL) configuration signals to allow the switching of clock modes or the bypass of the PLL without a hard reset operation. Clocking The TSPC106 requires a single system clock input, SYSCLK. The frequency of SYSCLK dictates the operating frequency of the PCI bus. An internal PLL on the TSPC106 generates a master clock that is used for all of the internal (core) logic. The master clock provides the core frequency reference and is phase-locked to the SYSCLK input. The 60x processor, L2 cache and memory interfaces operate at the core frequency. The PLL[0:3] signals configure the core-to-SYSCLK frequency ratio. The TSPC106 supports core-to-SYSCLK frequency ratios of 1:1, 2:1 and 3:1, although not all ratios are supported for all frequencies. The TSPC106 supports changing the clock mode and bypassing the PLL without requiring a hard reset operation, provided the system design allows sufficient time for the PLL to relock. Address Maps The TSPC106 supports three address mapping configurations designated address map A, address map B, and emulation mode address map. Address map A conforms to the "PowerPC Reference Platform Specification". Address map B conforms to the "PowerPC Common Hardware Reference Platform Architecture (CHRP)". The emulation mode address map is provided to support software emulation fx86 hardware. The configuration signal DBG0, sampled during power-on reset, selects between address map A and address map B. After reset, the address map can be changed by a programmable parameter. The emulation mode address map can only be selected by software after reset. 19 2102B-HIREL-02/02 Detailed Specifications Scope Applicable Documents This drawing describes the specific requirements of the TSPC106 in compliance with MIL-STD-883 class B or manufacturer's standard screening. Documents applicable to the information contained in this datasheet are: 1. MIL-STD-883: Test Methods and Procedures for Electronics 2. MIL-PRF-38535: General Specifications for Microcircuits Requirements General The microcircuits are in accordance with the applicable documents and as specified herein. Design and Construction Terminal Connections The terminal connections are as shown in "Pin Description" on page 4. Lead Material and Finish Lead material and finish are as specified in "Package Mechanical Data" on page 37. Package The macrocircuits are packaged in 303-pin ceramic ball grid array packages. The precise package drawings are described at the end of the specification. "CBGA Package Parameters" on page 37 and "CI_CGA Package Parameters" on page 38. Absolute Maximum Ratings Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Table 11. Absolute Maximum Ratings Symbol VDD AVDD VIN TSTG Notes: Parameter Supply Voltage PLL Supply Voltage Input Voltage Storage Temperature Range Min -0.3 -0.3 -0.3 -55 Max 3.6 3.6 5.5 +150 Unit V V V C 1. Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the absolute maximums listed may affect device reliability or cause permanent damage to the device. 2. Caution: Input voltage must not be greater than the VDD supply voltage by more than 2.5V at all times including during power-on reset. Thermal Characteristics This section provides thermal management information for the C4/CBGA package. Proper thermal control design is primarily dependent upon the system-level design. The use of C4 die on CBGA interconnect technology offers significant reduction in both the signal delay and the microelectronic packaging volume. Figure 5 shows the salient features of the C4/CBGA interconnect technology. The C4 interconnection provides both the electrical and the mechanical connections for the die to the ceramic substrate. 20 TSPC106 2102B-HIREL-02/02 TSPC106 After the C4 solder bump is reflowed, epoxy (encapsulant) is under-filled between the die and the substrate. Under-fill material is commonly used on large high-power die; however, this is not a requirement of the C4 technology. The package substrate is a multilayer-co-fired ceramic. The package-to-board interconnection is via an array of orthogonal 90/10 (lead/tin) solder balls on 1.27 mm pitch. During assembly of the C4/CBGA package to the board, the high-melt balls do not collapse. Figure 5. Exploded Cross-section CI_CGA Package Chip with C4 Encapsulant Ceramic Substrate BGA Joint Printed Circuit Board CBGA Package Internal Package Conduction Resistance For the C4/CBGA packaging technology, the intrinsic conduction thermal resistance paths are as follows: * * the die junction-to-case thermal resistance the die junction-to-lead thermal resistance These parameters are shown in Table 12. In the C4/CBGA package, the silicon chip is exposed; therefore, the package case is the top of the silicon. Table 12. Thermal Resistance Thermal Metric Junction-to-case thermal resistance Junction-to-lead (ball) thermal resistance Junction-to-lead (column) thermal resistance Effective Thermal Resistance 0.133C/W 3.8C/W (CBGA package) 4.0C/W (CI_CGA package) Figure 6 shows a simplified thermal network in which a C4/CBGA package is mounted on a printed-circuit board. Figure 6. C4/CBGA Package Mounted on a Printed Circuit Board External Resistance Radiation Convection Heat Sink Thermal Interface Material Internal Resistance Printed Circuit Board Die/Package Die Junction Package/Leads External Resistance Note: Radiation Convection Internal package resistance differs from external package resistance. 21 2102B-HIREL-02/02 Power Consumption The TSPC106 provides hardware support for four levels of power reduction - the doze, nap and sleep modes are invoked by register programming and the suspend mode is invoked by assertion of an external signal. The design of the TSPC106 is fully static, allowing internal logic states to be preserved during all power-saving modes. The following sections describe the programmable power modes provided by the TSPC106. This is the default power state of the TSPC106 following a hard reset with all internal functional units fully powered and operating at full clock speed. In this power-saving mode, all the TSPC106 functional units are disabled except for PCI address decoding, system RAM refreshing and 60x bus request monitoring (through BRn). Once the doze mode is entered, a hard reset, a PCI transaction referenced to system memory or a 60x bus request can bring the TSPC106 out of the doze mode and into the full-on state. If the TSPC106 is awakened for a processor or PCI bus access, the access is completed and the MC106 returns to the doze mode. The TSPC106's doze mode is totally independent of the power saving mode of the processor. Nap mode provides further power savings compared to doze mode. In nap mode, both the processor and the TSPC106 are placed in a power reduction mode. In this mode, only the PCI address decoding, system RAM refresh and the processor bus request monitoring are still operating. Hard reset, a PCI bus transaction referenced to system memory or a 60x bus request can bring the TSPC106 out of the nap mode. If the TSPC106 is awakened by a PCI access, the access is completed and the TSPC106 returns to the nap mode. If the TSPC106 is awakened by a processor access, the access is completed but the TSPC106 remains in the full-on state. When in the nap mode, the PLL is required to be running and locked to the system clock (SYSCLK). Sleep mode provides further power saving compared to the nap mode. As in nap mode, both the processor and the TSPC106 are placed in a reduced power mode concurrently. In sleep mode, no functional units are operating except the system RAM refresh logic, which can continue (optionally) to perform the refresh cycles. A hard reset or a bus request wakes the TSPC106 from sleep mode. The PLL and SYSCLK inputs may be disabled by an external power management controller (PMC). For additional power savings, the PLL can be disabled by configuring the PLL[0:3] signals into the PLL-bypass mode. The external PMC must enable the PLL, turn on SYSCLK and allow the PLL time to lock before waking the system from sleep mode. Suspend mode is activated through assertion of the SUSPEND signal. In suspend mode, the TSPC106 may have its clock input and PLL shut down for additional power savings. Memory refresh can be accomplished in two ways, either by using self-refresh mode DRAMs or by using the RTC input on the TSPC106. To exit the suspend mode, the system clock must be turned on in sufficient time to restart the PLL. After this time, SUSPEND may be negated. In suspend mode, all outputs (except memory refresh) are released to a high-impedance state and all inputs, including hard reset (HRST), are ignored. Full-power Mode Doze Mode Nap Mode Sleep Mode Suspend Mode 22 TSPC106 2102B-HIREL-02/02 TSPC106 Power Dissipation Table 13 provides figures on power consumption for the TSPC106. Table 13. Power Consumption Mode Full-on Mode Typical Maximum Doze Mode Typical Maximum Nap Mode Typical Maximum Sleep Mode Typical Maximum Suspend Mode Typical Maximum Notes: 1. 2. 3. 4. 140 190 220 270 W W 260 360 330 450 W W 1.0 1.2 1.1 1.4 W W 1.0 1.2 1.1 1.4 W W 1.2 1.4 2.2 2.4 W W SYSCLK/Core33/66 MHz SYSCLK/Core33/83.3 MHz Unit Power consumption for common system configurations assuming 50 pF loads. Suspend power saving mode assumes SYSCLK off and PLL in bypass mode. Typical power is an average value measured at VDD = AVDD = 3.30 V and TA = 25 C. Maximum power is measured at VDD = AVDD = 3.45 V and TA = 25 C. Marking The documents that define the marking are identified in the related reference documents. Each microcircuit is legibly and permanently marked with the following information as a minimum: * * * * * * Manufacturer logo Manufacturer part number Class B identification (if applicable) Date-code of inspection lot ESD identifier (if available) Country of manufacture 23 2102B-HIREL-02/02 Electrical Characteristics Table 14. Recommended Operating Conditions Characteristic Supply voltage PLL supply voltage Input voltage Die junction temperature Symbol VDD AVDD Vin Tj Value 3.3 165 mv Min 2.51 - Max 3.465 0 to 5.5 0 to 105 Unit V V V C The extended temperature parts have die junction temperature of -40 to 105C Notes General Requirements All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given in Table 15. Table 15. Clock DC Timing Specifications (VDD = 3.3V 5% dc, GND = 0V dc, -55C TC 125C) Symbol VIH VIL CVIH CVIL Iin ITSI VOH VOL VOH VOL Cin Notes: Characteristic Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input low voltage Input leakage current, V IN = 3.3V (1) Min 2 GND 2.4 GND Max 5.5 0.8 5.5 0.4 15.0 15.0 Unit V V V V A A V Hi-Z (off-state) leakage current, VIN = 3.3V (1) Output high voltage, IOH = -7 mA Output low voltage, IOL = 7 mA PCI 3.3V signaling output high voltage, IOH = -0.5 mA PCI 3.3V signaling output low voltage, IOL = 1.5 mA Capacitance, Vin = 0V, f = 1 MHz(2) 2.7 2.4 0.5 V V 0.3 7.0 V pF 1. Excludes test signals (LSSD_MODE and JTAG signals). 2. This value represents worst case 40 Ohm drivers (default value for Processor/L2 control signals CI, WT, GBL, TBST, TSIZ[02], TT[0-4], TWE, and TV) only. Other signals have lower default driver impedance and will support larger IOH and IOL. All drivers may optionally be programmed to different driver strengths. 3. Capacitance is periodically sampled rather than 100% tested. 24 TSPC106 2102B-HIREL-02/02 TSPC106 Dynamic Characteristics This section provides the AC electrical characteristics for the TSPC106. After fabrication, parts are sorted by maximum 60x processor bus frequency as shown in Table 16 and tested for conformance to the AC specifications for that frequency. These specifications are for operation between 16.67 and 33.33 MHz PCI bus (SYSCLK) frequencies. The 60x processor bus frequency is determined by the PCI bus (SYSCLK) frequency and the settings of the PLL[0:3] signals. All timings are specified relative to the rising edge of SYSCLK. Table 16 provides the clock AC timing specifications as defined in Figure 7. Clock AC Specifications Table 16. Clock AC Timing Specifications (VDD = 3.3V 5% dc, GND = 0V dc, -55C TC 125C) SYSCLK/Core 33/66 MHz Ref Characteristic 60x processor bus (core) frequency VCO frequency(1) SYSCLK frequency 1 2, 3 4 (1) (1) SYSCLK/Core 33/83.3 MHz Min 16.67 150 16.67 30.0 Max 83.3 400 33.33 60.0 2.0 40 60 200 100 Unit MHz MHz MHz ns ns % ps s Min 16.67 150 16.67 30.0 (2) Max 66 400 33.33 60.0 2.0 SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle measured at 1.4V(3) SYSCLK jitter(4) 106 internal PLL relock time (3, 5) 40 60 200 100 Notes: 1. The SYSCLK frequency and PLL[0:3] settings must be chosen so that the resulting SYSCLK (bus) frequency, CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL[0:3] signal description in "System Design Information" on page 33 for valid PLL[0:3] settings. 2. Rise and fall times for the SYSCLK input are measured from 0.4V to 2.4V. 3. Timing is guaranteed by design and characterization and is not tested. 4. The total input jitter (short-term and long-term combined) must be under 200 ps. 5. PLL-relock time is the maximum time required for PLL lock after a stable VDD, AVDD, and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently reenabled during the sleep and suspend power-saving modes. Also note that HRST must be held asserted for a minimum of 255 bus clocks after the PLL-relock time (100 ms) during the power-on reset sequence. Figure 7. SYSCLK Input Timing Diagram 1 4 SYSCLK VM VM 2 4 CVIH VM CVIL 3 Note: VM = Midpoint Voltage (1.4V) 25 2102B-HIREL-02/02 Input AC Specifications Table 17 provides the input AC timing specifications as shown in Figure 8 and Figure 9. Table 17. Input AC Timing Specifications (VDD = 3.3V 5% dc, GND = 0V dc, CL = 50 pF, -55C TC 125C) 66 MHz Ref 10a 10a 10a Characteristic Group I input signals valid to SYSCLK (input setup)(1, 2, 3) Group II input signals valid to SYSCLK (input setup)(1, 2, 4) Group III input signals valid to SYSCLK (input setup)(1, 2, 5) Group IV input signals valid to SYSCLK (input setup)(1, 2, 6) Group V input signals valid to SYSCLK (input setup)(7, 8) Group VI input signals valid to SYSCLK (input setup)(7, 9) 60x Bus Clock to group I - IV inputs invalid (input hold)(3, 4, 5, 6) SYSCLK to group V - VI inputs invalid (input hold)(8, 11b 9) 83.3 MHz Max Min 3.5 3.5 2.5 4.0 7.0 7.0 0 -0.5 255 x tSYSCLK +100 s 3 x tSYSCLK 1.0 ns ns Max Unit ns ns ns ns ns ns ns ns Min 4.0 3.5 3.0 5.0 7.0 7.0 0 -0.5 255 x tSYSCLK +100 s 3 x tSYSCLK 1.0 10a 10b 10b 11a HRST pulse width Mode select inputs valid to HRST (input setup)(10, 10c 11c Notes: 11, 12) HRST to mode select input invalid (input hold)(10, 12) 1. Input specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the 1.4V of the rising edge of the input SYSCLK. Input and output timings are measured at the pin. 2. Processor and memory interface signals are specified from the rising edge of the 60x bus clock. 3. Group I input signals include the following processor, L2 and memory interface signals: A[0:31], PAR[0:7]/AR[1:8],BR[0:4], BRL2, XATS, LBCLAIM, ADS, BA0, TV and HIT (when configured for external L2). 4. Group II input signals include the following processor and memory interface signals: TBST, TT[0:4], TSIZ[0:2], WT, CI, GBL, AACK and TA. 5. Group III input signals include the following processor and memory interface signals: DL[0:31] and DH[0:31]. 6. Group IV input signals include the following processor and L2 interface signals: TS, ARTRY, DIRTY_IN and HIT (when configured for internal L2 controller). 7. PCI 3.3 V signaling environment signals are measured from 1.65V (VDD/ 2) on the rising edge of SYSCLK to VOH = 3.0V or VOL = 0.3V. PCI 5V signaling environment signals are measured from 1.65V (VDD/ 2) on the rising edge of SYSCLK to VOH = 2.4V or VOL = 0.55V. 8. Group V input signals include the following bussed PCI interface signals: FRAME, C/BE[0:3], AD[0:31], DEVSEL, IRDY, TRDY, STOP, PAR, PERR, SERR, LOCK, FLSHREQ, and ISA_MASTER. 9. Group VI input signal is the point-to-point PCI GNT input signal. 10. The setup and hold time is with respect to the rising edge of HRST. Mode select inputs include the RCS0, FOE and DBG0 configuration inputs. 11. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds (ns). When the unit is given as tSYSCLK the numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 12. These values are guaranteed by design and are not tested. 26 TSPC106 2102B-HIREL-02/02 TSPC106 Figure 8. Input Timing Diagram VM SYSCLK 10a 10b 11a All Inputs Note: VM = Midpoint Voltage (1.4V) Figure 9. Mode Select Input Timing Diagram HRST 10c 11c VM MODE Pins Note: VM = Midpoint Voltage (1.4V) 27 2102B-HIREL-02/02 Output AC Specifications Table 18 provides the output AC timing specifications as shown in Figure 10. Table 18. Output AC Timing Specifications (VDD = 3.3V 5% dc, GND = 0V dc, C L = 50 pF, -55C TC 125C) 66 MHz Ref 12 13a 13b Characteristic SYSCLK to output driven (output enable time)(9) SYSCLK to output valid (for TS and ARTRY)(1, 2, 3, 4) SYSCLK to output valid (for all non-PCI signals except TS, ARTRY, RAS[0:7] and CAS[0:7]) and DWE[0:2](1, 2, 3, 5) SYSCLK to output valid (for RAS[0:7] and CAS[0:7])(1, 2, 3) SYSCLK to output valid (for PCI signals)(3, 6) SYSCLK to output invalid for all non-PCI signals (output hold)(7, 10) SYSCLK to output valid for PCI signals (output hold)(7) SYSCLK to ARTRY high impedance before precharge (output hold)(9) SYSCLK to ARTRY precharge enable(8, 9) SYSCLK to ARTRY high impedance after precharge(8, 9) (0.4 x tSYSCLK) + 2.0 (1.5 x tSYSCLK) + 8.0 1.0 1.0 8.0 (0.4 x tSYSCLK) + 2.0 (1.5 x tSYSCLK) + 8.0 Min 2.0 7.0 7.0 Max Min 2.0 6.0 6.0 83.3 MHz Max Unit ns ns ns 14a 14b 15a 15b 18 19 21 Notes: 7.0 11.0 1.0 1.0 6.0 11.0 ns ns ns ns 8.0 ns ns ns 1. Processor and memory interface signals are specified from the rising edge of the 60x bus clock. 2. Output specifications are measured from 1.4V on the rising edge of SYSCLK to the TTL level (0.8V or 2.0V) of the signal in question. Both input and output timings are measured at the pin. 3. The maximum timing specification assumes CL = 50 pF. 4. The shared outputs TS and ARTRY require pull-up resistors to hold them negated when there is no bus master driving them. 5. When the TSPC106 is configured for asynchronous L2 cache SRAMs, the DWE[0:2] signals have a maximum SYSCLK to output valid time of (0.5 x tPROC) + 8.0 ns (where tPROC is the 60x bus clock cycle time). 6. PCI 3.3V signaling environment signals are measured from 1.65V (VDD/ 2) on the rising edge of SYSCLK to VOH = 3.0V or VOL = 0.3V. 7. The minimum timing specification assumes CL = 50 pF. 8. tSYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as tSYSCLK, the numbers given in the table must be multiplied by the period of SYSCLK to compute the actual duration in nanoseconds of the parameter in question. 9. These values are guaranteed by design and are not tested. 10. PCI devices which require more than the PCI-specified hold time of TH = 0 ns or systems where clock skew approaches the PCI-specified allowance of 2 ns may not work with the TSPC106. For workarounds, see Motorola application note "Designing PCI 2.1-compliant MPC106 Systems" (order number AN1727/D). 28 TSPC106 2102B-HIREL-02/02 TSPC106 Figure 10. Output Timing Diagram VM SYSCLK 14 12 All Outputs (except TS and ARTRY) 15 13 TS 21 20 19 18 13 16 15 16 VM VM ARTRY Note: VM = Midpoint Voltage (1.4V) Table 19. JTAG AC Timing Specifications (Independent of SYSCLK) (VDD = 3.3V 5% dc, GND = 0V dc,C L = 50 pF, -55C TC 125C) Ref Characteristic TCK frequency of operation 1 2 3 4 5 6 7 8 9 10 11 12 13 Notes: 1. 2. 3. 4. TCK cycle time TCK clock pulse width measured at 1.4 V TCK rise and fall times TRST setup time to TCK rising edge TRST assert time Boundary-scan input data setup time (2) Boundary-scan input data hold time TCK to output data valid (3) (2) (1) Min 0 40 20 0 10 10 5 15 0 0 5 15 0 0 Max 25 Unit MHz ns ns 3 ns ns ns ns ns 30 30 ns ns ns ns TCK to output high impedance(3) TMS, TDI data setup time TMS, TDI data hold time TCK to TDO data valid TCK to TDO high impedance These values are guaranteed by design, and are not tested. TRST is an asynchronous signal. The setup time is for test purposes only. Non-test signal input timing with respect to TCK. Non-test signal output timing with respect to TCK. 15 15 ns ns 29 2102B-HIREL-02/02 Figure 11. JTAG Clock Input Timing Diagram 1 2 VM TCK 3 3 VM 2 VM Figure 12. TRST Timing Diagram TCK 4 TRST 5 Figure 13. Boundary-scan Timing Diagram TCK 6 Data Inputs 8 Data Outputs 9 Data Outputs 8 Data Outputs Output Data Valid Output Data Valid 7 Input Data Valid 30 TSPC106 2102B-HIREL-02/02 TSPC106 Figure 14. Test Access Port Timing Diagram TCK 10 TDI, TMS 12 TDO 13 TDO 12 TDO Output Data Valid Output Data Valid 11 Input Data Valid Architectural Overview 60x Processor Interface The TSPC106 supports a programmable interface to a variety of PowerPC microprocessors operating at select bus speeds.The address bus is 32 bits wide and the data bus is 64 bits wide. The 60x processor interface of the TSPC106 uses a subset of the 60x bus protocol, supporting single-beat and burst data transfers. The address and data buses are decoupled to support pipelined transactions. Two signals on the TSPC106, local bus slave claim (LBCLAIM) and data bus grant local bus slave (DBGLB), are provided for an optional local bus slave. However, the local bus slave must be capable of generating the transfer acknowledge (TA) signal to interact with the 60x processor(s). Depending on the system implementation, the processor bus may operate at the PCI bus clock rate or at two or three times the PCI bus clock rate. The 60x processor bus is synchronous with all timing relative to the rising edge of the 60x bus clock. Secondary (L2) Cache/Multiple Processor Interface The 106 provides support for the following configurations of 60x processors and L2 cache: * * * Up to four 60x processors with no L2 cache A single 60x processor plus a direct-mapped, lookaside, L2 cache using the internal L2 cache controller of the TSPC106 Up to four 60x processors plus an externally-controlled L2 cache The internal L2 cache controller generates the arbitration and support signals necessary to maintain a write-through or write-back L2 cache. The internal L2 cache controller supports either asynchronous SRAMs, pipelined burst SRAMs or synchronous burst SRAMs, using byte parity for data error detection. 31 2102B-HIREL-02/02 When more than one 60x processor is used, nine signals of the L2 interface change their functions (to BR[1:3], BG[1:3] and DBG[1:3]) to allow for arbitration between the 60x processors. The 60x processors share all 60x interface signals of the TSPC106, except the bus request (BR), bus grant (BG) and the data bus grant (DBG) signals. When an external L2 controller (or integrated L2 cache module) is used, three signals of the L2 interface change their functions (to BRL2, BGL2 and DBGL2) to allow the TSPC106 to arbitrate between the external cache and the 60x processor(s). Memory Interface The memory interface controls processor and PCI interactions to main memory. It is capable of supporting a variety of DRAM or extended data out (EDO) DRAM and ROM or Flash ROM configurations as main memory. The maximum supported memory size is 1-Gbyte of DRAM or EDO DRAM, with 16M bytes of ROM or Flash ROM. The memory controller of the TSPC106 supports the various memory sizes through software initialization of on-chip configuration registers. Parity or ECC is provided for error detection. The TSPC106 controls the 64-bit data path to main memory (72-bit data path with parity or ECC). To reduce loading on the data bus, system designers must implement buffers between the 60x bus and memory. The TSPC106 features configurable data/parity buffer control logic to accommodate several buffer types. The TSPC106 is capable of supporting a variety of DRAM/EDO configurations. DRAM/EDO banks can be built of SIMMS, DIMMs or directly-attached memory devices. Thirteen multiplexed address signals provide for device densities up to 16 Mbits. Eight row address strobe (RAS[0:7]) signals support up to eight banks of memory. The TSPC106 supports bank sizes from 2M bytes to 128M bytes. Eight column address strobe (CAS[0:7]) signals are used to provided byte selection for memory bank access (note that all CAS signals are driven in ECC mode). The TSPC106 provides parity checking and generation in two forms, normal parity and read-modify-write (RMW) parity. As an alternative to simple parity, the TSPC106tspc106 supports error checking and correction (ECC) for system memory. Using ECC, the TSPC106 detects and corrects all single-bit errors and detects all double-bit errors and all errors within a nibble (i.e., four bits or one-half byte). For ROM/Flash support, the TSPC106 provides 20 address bits (21 address bits for the 8-bit wide ROM interface), two bank selects, one output enable, and one Flash ROM write enable. The 16-Mbyte ROM space is subdivided into two 8-Mbyte banks. Bank 0 (selected by RCS0) is addressed from 0xFF80_0000 to 0xFFFF_FFFF. Bank 1 (selected by RCS1) is addressed from 0xFF00_0000 to 0xFF7F_FFFF. A configuration signal, flash output enable (FOE) sampled at reset, determines the bus width of the ROM or Flash device (8-bit or 64-bit) in bank 0. The data bus width for ROM bank 1 is always 64 bits. For systems using the 8-bit interface to bank 0, the ROM/Flash device must be connected to the most-significant byte lane of the data bus (DH[0:7]). The TSPC106 also supports a mixed ROM system configuration. That is, the system can have the upper 8M bytes (bank 0) of ROM space located on the PCI bus and the lower 8M bytes (bank 1) of ROM located on the 60x/memory bus. 32 TSPC106 2102B-HIREL-02/02 TSPC106 PCI Interface The TSPC106's PCI interface is compliant with the PCI Local Bus Specification, Revision 2.1, and follows the guidelines in the PCI System Design Guide, Revision 1.0 for host bridge architecture. The PCI interface connects the processor and memory buses to the PCI bus, to which I/O components are connected. The PCI bus uses a 32-bit multiplexed address/data plus various control and error signals. The PCI interface of the TSPC106 functions as both a master and target device. As a master, the TSPC106 supports read and write operations to the PCI memory space, the PCI I/O space, and the PCI configuration space. The TSPC106 also supports PCI special-cycle and interrupt-acknowledge commands. As a target, the TSPC106 supports read and write operations to system memory. Mode selectable big-endian to little-endian conversion is supplied at the PCI interface. Internal buffers are provided for I/O operation between the PCI bus and the 60x processor or memory. Processor read and write operations each have a 32-byte buffer and memory operation has one 32-byte read buffer and two 32-byte write buffers. System Design Information PLL Configuration This section provides electrical and thermal design recommendations for successful application of the TSPC106. The TSPC106 requires a single system clock input, SYSCLK. The SYSCLK frequency dictates the frequency of operation for the PCI bus. An internal PLL on the TSPC106 generates a master clock that is used for all of the internal (core) logic. The master clock provides the core frequency reference and is phase-locked to the SYSCLK input. The 60x processor, L2 cache and memory interfaces operate at the core frequency. In the 5:2 clock mode (Rev. 4.0 only), the TSPC106 needs to sample the 60x bus clock (on the LBCLAIM configuration input) to resolve clock phasing with the PCI bus clock (SYSCLK). The PLL is configured by the PLL[0:3] signals. For a given SYSCLK (PCI bus) frequency, the clock mode configuration signals (PLL[0:3]) set the core frequency (and the frequency of the VCO controlling the PLL lock). The supported core and VCO frequencies and the corresponding PLL[0:3] settings are provided in Table 19. 33 2102B-HIREL-02/02 Table 20. Core/VCO Frequencies and PLL Settings Core Frequency (VCO Frequency) in MHz PLL[0:3](1) 0010 0101 0110 0111 1000 1001 0011 Core/SYSCL Ratio 1:1 2:1 5:2 5:2 (2) (2) VCO Multiplier x8 x4 x2 x4 x2 x4 PCI Bus 16.6 MHz PCI Bus 20 MHz PCI Bus 25 MHz PCI Bus 33.3 MHz 33.3 (266) 40 (160) 50 (200) 66.6 (266) 83.3 (166) 41.6 (166) 50 (200) 62,5 (250) 75 (150) 83,3 (333) 3:1 3:1 PLL Bypass (3) 60 (240) 75 (300) PLL off SYSCLK clocks core circuitry directly 1 x core/SYSCLK ratio implied PLL off No core clocking occurs 1111 Clock off(4) Notes: 1. PLL[0:3] settings not listed are reserved. Some PLL configurations may select bus, CPU or VCO frequencies which are not useful, not supported or not tested. See "Input AC Specifications" on page 26 for valid SYSCLK and VCO frequencies. 2. 5:2 clock modes are only supported by TSPC106 Rev 4.0; earlier revisions do not support 5:2 clock modes. The 5:2 modes require a 60x bus clock applied to the 60x clock phase (LBCLAIM) configuration input signal during power-on reset, hard reset and coming out of sleep and suspend power saving modes. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal circuitry directly, the PLL is disabled and the core/SYSCLK ratio is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In clock-off mode, no clocking occurs inside the TSPC106 regardless of the SYSCLK input. 5. PLL[0:3] = 0010 (1:1 Core/SYSCLK Ratio; X8 VCO Multiplier) exists on the chip but will fail to lock 50% of the time. Therefore this configuration should not be used and 1:1 modes between 16 and 25 MHz are not supported. PLL Power Supply Filtering The AVDD power signal is provided on the 106 to provide power to the clock generation phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered using a circuit similar to the one shown in Figure 15. The circuit should be placed as close as possible to the AVDD pin to ensure it filters out as much noise as possible. Figure 15. PLL Power Supply Filter Circuit 10 VDD (3.3V) 10 F 0.1 F AVDD GND 34 TSPC106 2102B-HIREL-02/02 TSPC106 Decoupling Recommendations Due to the TSPC106's large address and data buses, and high operating frequencies, the TSPC106 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the system, and the TSPC106 itself requires a clean, tightly regulated source of power. It is strongly recommended that the system design include six to eight 0.1 F (ceramic) and 10 F (tantalum) decoupling capacitors to provide both high- and low-frequency filtering. These capacitors should be placed closely around the perimeter of the TSPC106 package (or on the underside of the PCB). It is also recommended that these decoupling capacitors receive their power from separate VDD and GND power planes in the PCB, utilizing short traces to minimize inductance. Only SMT (surface mount technology) capacitors should be used to minimize lead inductance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD plane, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are 100 F (AVX TPS tantalum) or 330 F (AVX TPS tantalum). Connection Recommendations To ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied (using pull-up resistors) to VDD. Unused active high inputs should be tied (using pull-down resistors) to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, AVDD and GND pins of the TSPC106. Pull-up Resistor Recommendations The TSPC106 requires pull-up (or pull-down) resistors on several control signals of the 60x and PCI buses to maintain the control signals in the negated state after they have been actively negated and released by the TSPC106 or other bus masters. The JTAG test reset signal, TRST, should be pulled down during normal system operation. Also, as indicated in Table 21, the factory test signal, LSSD_MODE, must be pulled up for normal device operation. During inactive periods on the bus, the address and transfer attributes on the bus (A[0:31], TT[0:4], TBST, WT, CI and GBL) are not driven by any master and may float in the high-impedance state for relatively long periods of time. Since the TSPC106 must continually monitor these signals, this float condition may cause excessive power draw by the input receivers on the TSPC106 or by other receivers in the system. It is recommended that these signals be pulled up or restored in some manner by the system. The 60x data bus input receivers on the TSPC106 do not require pull-up resistors on the data bus signals (DH[0:31], DL[0:31] and PAR[0:7]). However, other data bus receivers in the system may require pull-up resistors on these signals. In general, the 60x address and control signals are pulled up to 3.3 Vdc and the PCI control signals are pulled up to 5 Vdc through weak (2 - 10 k) resistors. Resistor values may need to be adjusted stronger to reduce induced noise on specific board designs. Table 21 summarizes the pull-up/pull-down recommendations for the TSPC106. 35 2102B-HIREL-02/02 Table 21. Pull-up/Pull-down Recommendations Signal Type 60x bus control 60x bus address/transfer attributes Cache control Signals BRn, TS, XATS, AACK, ARTRY, TA A[0:31], TT[0:4], TBST, WT, CI, GBL ADS HIT, TV PCI bus control REQ, FRAME, IRDY, DEVSEL, TRDY, STOP, SERR, PERR, LOCK, FLSHREQ, ISA_MASTER TRST LSSD_MODE Pull-up/Pull-down Pull-up to 3.3V dc Pull-up to 3.3V dc Pull-up to 3.3V dc Pull-up to 3.3V dc or pull-down to GND depending on programmed polarity Pull-up to 5V dc Note: For closed systems not requiring 5V power, these may be pulled up to 3.3 VDC. Pull-down to GND (during normal system operation) Pull-up to 3.3V dc JTAG Factory test Preparation for Delivery Packaging Certificate of Compliance Handling Microcircuits are prepared for delivery in accordance with MIL-PRF-38535. Atmel offers a certificate of compliance with each shipment of parts, confirming that the products are in compliance with MIL-STD-883 and guaranteeing the parameters not tested at temperature extremes for the entire temperature range. MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: * * * * * * Devices should be handled on benches with conductive and grounded surfaces. Ground test equipment, tools and operator. Do not handle devices by the leads. Store devices in conductive foam or carriers. Avoid use of plastic, rubber or silk in MOS areas. Maintain relative humidity above 50% if practical. 36 TSPC106 2102B-HIREL-02/02 TSPC106 Package Mechanical Data CBGA Package Parameters Table 22. CBGA Package Parameters Parameter Package outline Interconnects Pitch Solder attach Solder balls Maximum module height Co-planarity specification Min 21 mm x 25 mm 303 (16 x 19 ball array minus one) 1.27 mm 63/37 Sn/Pb 10/90 Sn/Pb, 0.89 mm diameter 3.16 mm 0.15 mm Max Parameter A B C D G H K N P 5.8 7.2 0.79 0.635 BASIC 6.0 7.4 2.3 0.82 1.27 BASIC 0.99 Min 25.0 0.2 21.0 0.2 3.16 0.93 Max Figure 16. CBGA Mechanical Drawing 2X -F- 0.200 Br A1 -E- *Not to scale Top view -T- A P 0.150 T 2X 0.200 N 1 2 3 4 5 6 7 8 9 1011 1213141516 W V U T R P N M L K J H G F E D C B A Bottom View C H G AE 0.300 S 303X AE D AE 0.150 S TES T F S G K 37 2102B-HIREL-02/02 CI_CGA Package Parameters Table 23. CI-CGA Package Parameters Parameter Package outline Interconnects Pitch Solder attach Solder balls Maximum module height Co-planarity specification Min 21 mm x 25 mm 303 (16 x 19 ball array minus one) 1.27 mm 63/37 Sn/Pb 10/90 Sn/Pb, 0.89 mm diameter 3.84 mm 0.15 mm Max Parameter A B C D G H K N P 1.545 0.635 BASIC 6.2 BASIC 7.6 BASIC 0.79 1.27 BASIC 1.695 Min 25.0 BASIC 21.0 BASIC 3.84 BASIC 0.99 Max Figure 17. CI_CGA Mechanical Drawing 2X -F- 0.200 Br A1 -E- *Not to scale Top view -T- A P 0.150 T 2X 0.200 N 1 2 3 4 5 6 7 8 9 1011 1213141516 W V U T R P N M L K J H G F E D C B A Bottom View C H G 0.300 S 303X D 0.150 S TES T F S G K 38 TSPC106 2102B-HIREL-02/02 TSPC106 Ordering Information TS Manufacturer's Prefix Type Temperature Range: TC M: -55 C, +125 C V: -40 C, +110 C Package G: CBGA GS: CI_CGA PC106A M GS B/Q 66 CG Revision Level(1) CE: Rev. 3.0 CG: Rev. 4.0 Operating Frequency(1) 66: 66 MHz 83: 83.3 MHz Screening Level(1) _: Standard B/Q: MIL-STD-883, Class Q B/T: According to MIL-STD-883 U: Upscreening U/T: Upscreening + burn-in Note: For availability of different versions, contact your Atmel sales office. 39 2102B-HIREL-02/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 RF/Automotive Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 ASIC/ASSP/Smart Cards Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademarks of Atmel. PowerPC (R) is the registered trademark of IBM Company. Other terms and product names may be the trademarks of others. 2102B-HIREL-02/02 0M |
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